When the p-type and the n-type materials are kept in contact with
each other, the junction between them behaves differently from either
side of the material alone. The electrons and holes are close to each
other at the junction. According to coulomb’s law, there is a force
between the negative electrons and the positive holes. When the p-n
junction is formed a few electrons from the n-type diffuse through the
junction and combines with the holes in the p-side to form negative ions
and leaves behind positive ions in the n-side. This results in the
formation of the depletion layer, which acts as the barrier and does not
allow any further flow of electrons from the n region to the p
region.
No Applied Bias(V = 0V)
no-bias
在没有外部电压的情况下，depletion region正常存在。n
type这边主要载流子是电子，但是如果要流向p type，需要克服正电子的吸引，所以只有一小部分能够过去，这个数量和从p
type流过来的电子（少数载流子）数目接近，也就是图12 c 左上的和右下的正好差不多抵消。同理两个也差不多。所以总体电流为0。
In the absence of an applied bias across a semiconductor
diode, the net flow of charge in one direction is zero.
The current that exists under reverse-bias conditions is
called the reverse saturation current and is represented by .
Foward-Bias Condition()
foward-bias
当正向电压的时候，首先depletion region会变薄，因为n
type这边会有大量电子注入，重新和正电子结合，p
type的电子会被“抽走”。当电压加到一定程度，突然大量电子从n涌入p，图12 c
右下的是会不断增大。
is the reverse saturation
current
is the applied forward-bias
voltage across the diode
n is an ideality factor, which is a function of the
operating conditions and physical construction; it has a range between 1
and 2 depending on a wide variety of factors (n =1 will be
assumed throughout this text unless otherwise noted).
k is Boltzmann’s constant =
is the absolute temperature
in kelvins = 273 + the temperature in
q is the magnitude of electronic charge =
diode-characteristics
虚线是理想的曲线，实现是实际的情况。
The actual reverse saturation current of a commercially
available diode will normally be measurably larger than that appearing
as the reverse saturation current in Shockley’s equation.
反向的饱和电流实际会在理想的下方，主要原因是：
– leakage currents
– generation of carriers in the depletion
region
– higher doping levels that result in increased
levels of reverse current
– sensitivity to the intrinsic level of carriers
in the component materials by a squared
factor—double the intrinsic level, and the contribution to the
reverse current could
increase by a factor of four.
– a direct relationship with the junction
area—double the area of the junction, and
the contribution to the reverse current could double. High-power
devices that have
larger junction areas typically have much higher levels of reverse
current.
– temperature sensitivity—for every 5°C increase
in current, the level of reverse sat- uration current in Eq. 1 will
double, whereas a 10°C increase in current will result in
doubling of the actual reverse current of a diode.
The farther an electron is from the nucleus, the higher is
the energy state, and any electron that has left its parent atom has a
higher energy state than any electron in the atomic
structure.
energy-gap
Only specific energy levels can exist for the electrons in the atomic
structure of an isolated atom. The result is a series of gaps between
allowed energy levels where carriers are not permitted.
energy-levels
There is a minimum energy level associated with electrons in the
conduction band and a maximum energy level of electrons bound to the
valence shell of the atom. Between the two is an energy gap that the
electron in the valence band must overcome to become a free carrier.
That energy gap is different for Ge, Si, and GaAs; Ge has the smallest
gap and GaAs the largest gap. In total, this simply means that:
An electron in the valence band of silicon must absorb more
energy than one in the valence band of germanium to become a free
carrier. Similarly, an electron in the valence band of gallium arsenide
must gain more energy than one in silicon or germanium to enter the
conduction band.
Ge devices:
photodetectors sensitive to light
security system sensitive to heat
Si and GaAs:
transistor networks, stability is a high priority
The wider the energy gap, the greater is the possibility of energy
being released in the form of visible (infrared) light waves. For GaAs
the gap is sufficiently large to result in significant light
radiation.
The units of measurement are electron volts (eV). The unit
of measure is appropriate because W (energy) = QV (as
derived from the defining equation for voltage: V =
W/Q). Substituting the charge of one electron and a
potential difference of 1 V results in an energy level referred to as
one electron volt.
As indicated in Fig. 3, silicon has 14 orbiting electrons, germanium
has 32 electrons, gallium has 31 electrons, and arsenic has 33 orbiting
electrons.
For germanium and silicon there are four electrons in the outermost
shell, which are referred to as valence electrons.
Valence electrons are electrons in the outer shells that are not
filled. Because valence electrons have higher energy than electrons in
inner orbits, they are involved in the majority of chemical processes.
They assist us in determining the chemical properties of an element,
such as its valency or how it forms bonds with other elements.
Gallium has three valence electrons and arsenic has five valence
electrons. Atoms that have four valence electrons are called
tetravalent, those with three are called trivalent,
and those with five are called pentavalent.
The term valence is used to indicate that the potential
(ionization potential) required to remove any one of these electrons
from the atomic structure is significantly lower than that required for
any other electron in the structure.
Ionization energy, also called ionization potential, is the energy
necessary to remove an electron from the neutral atom. X + energy → X+ +
e− where X is any atom or molecule capable of being ionized, X + is that
atom or molecule with an electron removed (positive ion), and e − is the
removed electron.
covalent-bonding
In a pure silicon or germanium crystal the four valence electrons of
one atom form a bonding arrangement with four adjoining atoms, as shown
in Fig. 4.
This bonding of atoms, strengthened by the sharing of
electrons, is called covalent bonding.
Because GaAs is a compound semiconductor, there is sharing between
the two different atoms, as shown in Fig. 5. Each atom, gallium or
arsenic, is surrounded by atoms of the complementary type. There is
still a sharing of electrons similar in structure to that of Ge and Si,
but now five electrons are provided by the As atom and three by the Ga
atom.
covalent-binding-gaas
Although the covalent bond will result in a stronger bond between the
valence electrons and their parent atom, it is still possible for the
valence electrons to absorb sufficient kinetic energy from external
natural causes to break the covalent bond and assume the “free” state.
The term free is applied to any electron that has separated
from the fixed lattice structure and is very sensitive to any applied
electric fields such as established by voltage sources or any difference
in potential. The external causes include effects such as light
energy in the form of photons and thermal energy (heat) from the
surrounding medium. At room temperature there are approximately
free carriers in
of intrinsic
silicon material, that is, 15,000,000,000 (15 billion) electrons in a
space smaller than a small sugar cube—an enormous number.
The central processing unit(CPU) always starts in real mode, and then
the main loader usually executes the code to explicitly switch it to
protected mode and then to the long mode.
These are the registers usable in real mode:
ip, flags;
ax, bx, cx, dx, sp, bp, si, di;
Segment registers: cs, ds, ss, es, (later also gs and fs).
As it was not straightforward to address more than 64 Kilobytes of
memory, engineers came up with a solution to use special
segement registers in the following way:
Each physical address consists of 20 bits(so, 5 hexadecimal
digits).
Each logical address consists of two components. One is taken
from a segment register and encodes the segment start. The other is an
offset inside this segment. The hardware calculates the physical address
from these components the following way:
physical address = segment base * 16 + offset
You can often see addresses written in form of segment:offset, for
example:
1
4a40:0002, ds:0001, 7bd3:ah
Note that strictly speaking, the segment register do not hold
segments' starting addresses but rather their parts(the four most
significant hexadecimal digits). By adding another zero digit to
multiply it by we get the
real segment starting address.
Each instruction referencing memory implicitly assumes usage of one
of segment registers. Documentation clarifies the default segment
registers for each instruction. However, common sense can help as well.
For instance, mov is used to manipulate data, so the address is relative
to the data segment.
1
mov al, [0004] ; === mov al, ds:04444
It is possible to redefine the segment explicitly:
1
mov al, cs:[0004]
When the program is loaded, the loader set ip, cs, ss, and sp
register to that cs:ip corresponds to the entry point, and ss:sp points
on top of the stack.
Real mode has numerous drawbacks
It makes multitasking very hard. The same address space is shared
between all programs, so they should be loaded at different addresses.
Their relative placement should usually be decided during compilation.
:joy: But maybe we can distributed these tasks by hand.
Programs can rewrite each other's code or even operating system as
they all live in the same address space. :dog: What about only one
user?
Any program can execute any instruction, including those used to set
up the processor's state. Some instructions should only be used by the
operating system(like those used to set up virtual memory, perform power
management, etc.) as their incorrect usage can crash the whole system.
:laughing: We do not have operating system!
Protected Mode
Intel 80386 was the first processor implementing protected 32-bit
mode.
It provides wider versions of registers(eax, ebx, ..., esi, edi) as
well as new protection mechanisms: protection rings, virtural memory,
and an improved segmentation.
Obtaining a segment starting address has changed.
Linear address = segment base(taken from system table) + offset
Each of segment registers cs, ds, ss, es, gs, and fs stores so-called
segment selector, containing an index in a special
segment descriptor table and a little additional information.
Two types of segment descriptor tables:
LDT(Local Descriptor Table)
GDT(Global Descriptor Table)
segment-selector
Index denotes descriptor position in either GDT or LDT. The T bit
select either LDT or GDT. As LDTs are no longer used, it will be zero in
all cases.
The table entries in GDT/LDT also store information about which
privilege level is assigned to the described segment. When a segment is
accessed through segement selector, a check of Request Privilege
Level(RPL) value(stored in selector = segment register) against
Descriptor Privilege Level(stored in descriptor table) is performed. If
RPL is not privileged enough to access a high privileged segment, an
error will occur. This way we could create numerous segments with
various permissions and use RPL values in segment selectors to define
which of them are accessible to us right now(given our privilege
level).
segment-descriptor
G-Granularity, e.g., size is in 0=bytes, 1=pages of size 4096 bytes
each.
D-Default operand size(0=16 bit, 1=32 bit).
L-Is it a 64-bit mode segment?
V-Available for use by system software.
P-Present in memory right now.
S-Is it data/code (1) or is it just some system information holder
(0).
X-Data (0) or code (1).
RW-For data segment, is writing allowed? (reading is always allowed);
for code segment, is reading allowed? (writing is always
prohibited).
DC-Growth direction: to lower or to higher addresses? (for data
segment); can it be executed from higher privilege levels? (if code
segment)
A-Was it accessed?
DPL-Descriptor Privilege Level (to which ring is it attached?)
mov eax, cr0 ; !! Privileged instruction or al, 1 ; this is the bit responsible for protected mode mov cr0, eax ; !! Privileged instruction jmp (0x1 << 3):start32 ; assign first seg selector to cs align 16 _gdtr: ; stores GDT's last entry index + GDT address dw 47 dq _gdt
align 16
_gdt: ; Null descriptor (should be present in any GDT) dd 0x00, 0x00 ; x32 code descriptor: db 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x9A, 0xCF, 0x00 ; differ by exec bit ; x32 data descriptor: db 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x92, 0xCF, 0x00 ; execution off (0x92) ; size size base base base util util|size base
As you see, writing in 8-bit or 16-bit parts leaves the rest of bits
intact. Writing to 32-bit parts, however, fill the upper half of a wide
register with sign bit!
Explanation
Let's think about instruction decoding. The part of a CPU called
instruction decoder is constantly translating commands from an older
CISC system to a more convenient RISC one. Pipelines allow for a
simultaneous execution of up to six smaller instructions. To achieve
that, however, the notion of registers should be virtualized. During
microcode execution, the decoder choose an available register from a
large bank of physical registers. As soon as the bigger instruction
ends, the effects become visible to programmer: the value of some
physical registers may be copied to those, currently assigned to be,
let's say, rax.
The data interdependencies between instructions stall the pipeline,
decreasing performance. The worst cases occur when the same register is
read and modified by several consecutive instructions(think about
rflags!).
If modifying eax means keeping upper bits of rax intact, it
introduces an additional dependency between current instruction and
whatever instruction modified rax or its parts before. By discarding
upper 32 bits on each write to eax we eliminate this dependency, because
we do not care anymore about previous rax value or its parts.
This kind of a new behavior was introduced with the latest general
purpose registers' growth to 64 bits and does not affect operations with
their smaller parts for the sake of compatibility. Otherwise, most older
binaries would have stopped working because assigning to, for example,
bl, would have modified the entire ebx, which was not true back when
64-bit registers had not yet been introduced.
